XilinxUltraScalePlus Member List

This is the complete list of members for XilinxUltraScalePlus, including all inherited members.

assembler(std::string, std::string)	XilinxUltraScalePlus
assemblerAsmTo(std::ifstream &, std::ofstream &)	XilinxUltraScalePlus
assemblerAsmToBin(std::ifstream &, std::ofstream &)	XilinxUltraScalePlus
assemblerAsmToBit(std::ifstream &, std::ofstream &)	XilinxUltraScalePlus
assemblerParseHeader(std::ifstream &)	XilinxUltraScalePlus
bitstreamBegin	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
bitstreamBRAM	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
bitstreamCLB	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
bitstreamEnd	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
bitstreamHasValidData	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
blank(std::string)	XilinxUltraScalePlus
change(std::string)	XilinxUltraScalePlus
CommonDevice()	CommonDevice	inline
CommonDevice2D()	CommonDevice2D	inline
designName	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
deviceHelp()	XilinxUltraScalePlus
disassemblerBinToAsm(std::string, std::ifstream &, std::ofstream &)	XilinxUltraScalePlus
disassemblerBitToAsm(std::ifstream &, std::ofstream &)	XilinxUltraScalePlus
disassemblerToAsm(std::ifstream &, std::ofstream &)	XilinxUltraScalePlus
disassemblerWriteHeader(std::ofstream &)	XilinxUltraScalePlus
enableLog	CommonDevice
enableWarn	CommonDevice
ensureInitializedBitstreamArrays() override	XilinxUltraScalePlus	virtual
fileDate	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
fileTime	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
fromRow	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
getDeviceByIDCODE(int) override	XilinxUltraScalePlus	virtual
getDeviceByIDCODEorThrow(int) override	XilinxUltraScalePlus	virtual
getDeviceByName(std::string) override	XilinxUltraScalePlus	virtual
getDeviceByNameOrThrow(std::string) override	XilinxUltraScalePlus	virtual
getFrameType(int, int, int) override	XilinxUltraScalePlus	virtual
headerLocationOfRemainingFileLength	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
IDCODE	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
initFabric()	XilinxUltraScalePlus
initializedBitstreamParamsShortPartName	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
initializedBitstreamShortPartName	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
initializedResourceStringShortPartName	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
initializeResourceStringParameters() override	XilinxUltraScalePlus	virtual
instanceName	CommonDevice
loadedBitstreamEndianness	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
log(std::string message)	CommonDevice	inline
LUT_isFrameUnusedForResourceLetter	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
LUT_numberOfFramesForResourceLetter	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
LUT_typeOfFrameForResourceLetter	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
maxNumberOfBRAMCols	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
maxNumberOfCols	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
merge(XilinxUltraScalePlus *, std::string, Rect2D, Coord2D)	XilinxUltraScalePlus
MergeOP enum name	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfBRAMCols	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfBRAMsBeforeCol	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfCols	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfFramesBeforeCol	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfFramesPerRow	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfRows	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfSLRs	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
numberOfWordsPerRow	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
outputBitstreamEmptySLRHeaderSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamEmptySLRWrapUpSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamGlobalFooterSequence(std::ofstream &, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamGlobalHeaderSequence(std::ofstream &, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamSLRFooterBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamSLRHeaderAfterBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamSLRHeaderBitstreamSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScalePlus	virtual
outputBitstreamSLRWrapUpSequence(std::ofstream &, int, bool, Endianness) override	XilinxUltraScalePlus	virtual
partName	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
printMessage(std::string message)	CommonDevice	inline
readBitstream(std::string)	XilinxUltraScalePlus
region(std::string, Rect2D)	CommonDevice2D
regionSelection	CommonDevice2D
resourceString	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
rowsInBottomHalf	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
rowsInTopHalf	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
selectedOptions	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
setDevice(int, std::string="") override	XilinxUltraScalePlus	virtual
setDeviceByIDCODEOrThrow(int) override	XilinxUltraScalePlus	virtual
setDeviceByNameOrThrow(std::string) override	XilinxUltraScalePlus	virtual
setDeviceByPartNameOrThrow() override	XilinxUltraScalePlus	virtual
SLRinfo	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
slrMagicInstrLocation	XilinxUltraScalePlus
test(bool, bool, uint32_t)	XilinxUltraScalePlus
toRow	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >
warn(std::string message)	CommonDevice	inline
writeBitstream(std::string, std::string, Rect2D)	XilinxUltraScalePlus
XilinxConfigurationAccessPort()	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >	inline
XilinxUltraScalePlus()	XilinxUltraScalePlus
~CommonDevice()	CommonDevice	inlinevirtual
~CommonDevice2D()	CommonDevice2D	inlinevirtual
~XilinxConfigurationAccessPort()	XilinxConfigurationAccessPort< 4, 20, 1024, 16, 2, 0, 1, 45, 3, 45,(45+3+45), 256, 60, 12, 2, 0, 0, 24, 0x7, 18, 0x3F, 8, 0x3FF, 0, 0xFF >	inlinevirtual
~XilinxUltraScalePlus()	XilinxUltraScalePlus	virtual